We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.

This paper describes a 28GHz CMOS direct conversion transceiver with packaged 2×4 patch antenna arrays for 5G communication. Test results show good RF performances of Rx NF 6.7dB, Maximum Tx EIRP 31.5dBm (1PA Pout_sat =10.5dBm), LO integrated phase noise −37.8dBc (0.67°), Rx/Tx EVM around 2.2% (−33.1dB) at mid RF power, and well-fitted beam control capability.

Hong-Teuk Kim, Principal Research Engineer LG Electronics, Seoul

Areas of interest: RF Circuit Development Leader -CDMA HBT PA MMIC, -Internal Antenna, -TV tuner, 2/3/4G transceiver,5G transceiver, -Antenna array design for beamforming, -Beamforming scenario and its adaptation to RF chip and antenna array, -5G package design with antenna array -RF sensor (nW wake-up and ..)

A 14nm FinFET CMOS 12-b current-steering digital-to-analog (DAC) for 2G/3G/4G cellular applications is presented. A bit segmentation of 6-bit thermometer and 6-bit binary is adopted, and it utilizes the dynamic element matching (DEM) technique to suppress the spurious tones caused by the current source mismatches in 3-D FinFETs. In addition, to keep the voltage drop across each transistor within long-term reliability limit, output switches are designed with shielding transistors while achieving make-before-break operation with the proposed low crossing point level shifter. The active area of a single DAC is 0.036 mm2, and its power consumption is 6.1 mW with SFDR of 80 dBc.

We present a SiGe BiCMOS fully integrated 7583 GHz FMCW synthesizer for automotive radar applications. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism was incorporated in a dual path PLL, providing low loop bandwidth variation over the whole output frequency range, 97 dBc/Hz phase noise at 1 MHz offset and maximum chirp rate of 100 GHz/mSec.

A wireless system-on-chip with integrated antenna, power harvesting and biosensors is presented that is small enough, 200m 200m 100m, to allow painless injection. Small device size is enabled by: a 13m 20m 1nA current reference; optical clock recovery; low voltage inverting dc-dc to enable use of higher quantum efficiency diodes; on-chip resonant 2.4GHz antenna; and array scanning reader. In-vivo power and data transfer is demonstrated and linear glucose concentration recordings reported.

This paper presents the design of an E-band PA in Intel 14nm FinFET/trigate CMOS process. Device layout optimizations are used to maximize device performance at mm-wave frequencies and overcome the impact of scaling on RF performance. Neutralization and low-k transformer-based matching networks are employed to improve gain and bandwidth. The PA achieves a peak gain of 11.9dB/16.7 dB at 71GHz with a bandwidth of 8.5GHz/7.4 GHz in low-gain/high-gain mode. At 71GHz, the measured Psat, OP1dB and peak PAE are 7.3dBm, 1.6dBm, and 8.3%, respectively. StevenCallender Intel, USA

A 2.4GHz fully-integrated Wi-Fi compliant wake-up receiver in 14nm FinFET technology is presented. The receiver achieves 72dBm sensitivity and +20dBr adjacent channel interference rejection for 62.5kbps at 103 BER while consuming 95W. The OOK-modulated wake-up packet can be transmitted using any legacy OFDM Wi-Fi transmitter.

An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and a fully-digital polar transmitter is presented. For the receiver, a current-mode RF front-end covers the mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains and bandwidths with an automatic gain/DC-offset calibration. Implemented in 40nm CMOS with 1V supply, this receiver achieves 104dBm sensitivity in the 1MHz MCS0 mode (i.e., 300kbp/s). It fulfils the adjacent channel rejection requirements with at least 17dB margin. The digital polar transmitter achieves 31dB EVM and 10dB spectral mask margin.

In this paper we present a chip-set of 4 wideband SiGe BiCMOS transceivers optimized for the stringent specifications of various microwave links in the 544 GHz range. Each receiver and transmitter covers full frequency bands of 5.68.5 GHz, 1015.5 GHz, 17.526.5 GHz and 2743.5 GHz and demonstrates high dynamic range and excellent noise figure and linearity. Radio links demonstrate error-free operation for channel bandwidths from 7 up to 112 MHz and modulations up to 4096 QAM.

The need for high-frequency, low-power, wide temperature range, precision on-chip reference clock generation makes relaxation oscillator topology an attractive solution for various automotive applications. This paper presents for the first time a 140MHz relaxation oscillator with robust-against-process-variation temperature compensation scheme. The high-frequency relaxation oscillator achieves 28 ppm/C frequency stability over the automotive temperature range from -40 to 175C. The circuit is fabricated in 40nm CMOS technology, occupies 0.009mm2 and consumes 294W from 1.2V supply